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W55VG680 TV ENCODER
W55VG680
Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 1 APPLICATION ............................................................................................................................ 1 PIN ARRANGEMENT ................................................................................................................. 2 PIN DESCRIPTION..................................................................................................................... 3 BLOCK DIAGRAM ...................................................................................................................... 5 FUNCTIONAL DESCRIPTION.................................................................................................... 6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8. 9. 10. 11. 12. Input formatting ............................................................................................................... 6 Mode selection................................................................................................................ 6 The Relationship between TV System and Bit allocation ............................................... 8 Color Space Conversion................................................................................................. 8 Low-Pass Filter ............................................................................................................... 8 Modulator ........................................................................................................................ 8 Video Timing ................................................................................................................... 9 Video and Burst Blanking ............................................................................................... 9 Power Down.................................................................................................................... 9 Analog outputs ................................................................................................................ 9
ELECTRICAL CHARACTERISTICS......................................................................................... 13 DC CHARACTERISTICS .......................................................................................................... 14 AC CHARACTERISTICS .......................................................................................................... 15 PACKAGE INFORMATION....................................................................................................... 22 PACKAGE DIMENSION ........................................................................................................... 23 12.1 12.2 PLCC ............................................................................................................................ 23 QFN-32 ......................................................................................................................... 24
13. 14. 15.
APPLICATION CIRCUIT........................................................................................................... 25 BILL OF MATERIAL.................................................................................................................. 26 DOCUMENT HISTORY ............................................................................................................ 26
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
1. GENERAL DESCRIPTION
The W55VG680 digital video encoder converts YCrCb (4:2:2) 8-bit data into analog composite video and Y/C video signals. The video format is 525-line (M) NTSC/PAL or 625-line (B, D, G, H, I, M, Nc) PAL. The W55VG680 can operate at master or slave mode. The data rate can be CCIR601 or square pixel. At slave mode, the W55VG680 can auto detect the input video format from the HSYNC and VSYNC pins and generates the corresponding video signals. At master mode, it generates the required video timing internally according to the configuration. The input YCrCb data are converted into YUV signals. The chroma data are then low passed by a 1.3 MHz filter and modulated by a color subcarrier. The W55VG680 operates with a 2X pixel rate input. The W55VG680 has two DAC outputs which can output two composite video or Y/C S-video signal. The W55VG680 can operate at power-down mode by selecting the SLEEP pin. The W55VG680 is designed for digital video applications such as VCD, DVD, and video games.
2. FEATURES
Monolithic CMOS process Master clock rate 2X pixel rate Two composite outputs or Y/C video output (S video) Power-down mode CCIR601 or square pixel input data rates Master/slave sync signal switchable Interlaced and non-interlaced operation Optional internal voltage reference
3. APPLICATION
For mobile phone image show on TV application
P[7:0] CLK W99802 HSYNCN VSYNCN W55VG680 CVBS/ C
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
4. PIN ARRANGEMENT
QFN package
PLCC package
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W55VG680
5. PIN DESCRIPTION
(All digital pins are TTL compatible)
PLCC PIN NO. QFN PIN NO. PIN NAME I/O DESCRIPTION
1
29
HSYNC
I/O
Horizontal synchronization input/output. In master mode, this pin generates vertical synchronizations signal from internal. In slave mode, the signals are from external. HSYNCN is latched/output following the rising edge of CLK. Test pin. These pins must be connected to DGND. No connection. Full-Scale adjust control pin. The Full-Scale current of D/A converters can be adjusted by connecting a resistor (RSET) between this pin and ground. The relationship is
Re xt ( ) = 4080 * VREF (V ) / Iout ( mA )
2 3, 4, 8, 10
30 4, 6, 31, 32
TEST N.C.
I ---
5
1
FSADJ
---
6 7
2 3
COMP VAA
-----
Compensation pin. A 0.1uF ceramic capacitor must be used to bypass this pin to VAA. The lead length must be kept as short as possible to avoid noise. Analog power pin Voltage reference output. It generates typical 1.2V for internal voltage reference. A 0.1uF ceramic capacitor must be used to decouple this input to GND. The decoupling capacitor must be as close as possible to minimize the length of the load. Composite/Chroma output. This is a high impedance current source Output. The output format can be selected by the PAL pin. The pin can drive a 37.5 mW load. If unused, this pin must be connected directly to GND. Analog ground pin Power save mode. A logical high on this pin puts the chip into power-down mode. SVIDEO select input pin. A logical high selects Y output. A logic low selects composite video output. Cr and Cb pixel sequence set up pin. A logical high swap the Cr and Cb sequence.
9
5
VREF
I/O
11
7
CVBS_C
O
12 13 14 15
8 9 10 11
AGND SLEEP SVIDEO CBSWAP
--I I I
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W55VG680
Pin Description, continued.
PLCC PIN NO.
QFN PIN NO.
PIN NAME
I/O
DESCRIPTION
16 17-20 21-28 29 30 31
12 13-16 17-24 25 26 27
MASTER Mode[3:0] P[0:7] CLK DGND VDD
I I I I -----
Master/slave mode select. A logical high for master mode operation. A logical 0 for slave mode operation Mode configuration pin. YCrCb pixel inputs. They are latched on the falling edge of CLK. YCrCb input data conform to CCIR 601. 2XPixel clock input for 8-bit YCrCb data. Digital ground pin Digital power pin Vertical synchronization input/output. In master mode, this pin generates vertical synchronizations signal from internal. In slave mode, the signals are from external. VSYNCN is latched/output following the rising edge of CLK.
32
28
VSYNC
I/O
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W55VG680
6. BLOCK DIAGRAM
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
7. FUNCTIONAL DESCRIPTION
7.1 Input formatting
The input circuitry accepts 8-bit CCIR601 4:2:2 YCrCb data . The data are input via the P[7:0] inputs and latched on the falling edge of CLK. The input YCrCb pixel sequence can be arranged by setting the CBSWAP pin and the YCSWAP mode register. If the CBSWAP pin and the YCSWAP mode register are all zero, the first pixel data latched by the CLK pin after the falling edge of HSYNCN is Cb. The sequence appears as Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 .... This can be swap by setting the CBSWAP pin and the YCSWAP mode register. The input clock rate can be CCIR601 2X13.5MHz or square pixel rate . Color burst frequency is derived from the CLOCK input. Any jitter on the CLOCK pin may induce a color burst frequency error. A stable clock source is recommended. The Y of the 16-bit YCrCb data has nominal range from 16-235 and Cr/Cb has a nominal range from 16-240, with 128 equal to zero. When the Y value is between 1-15, the internal circuit will clamp these values to 16. When the Y value is 0 and 255, the internal circuit will set the Y value as 38. When the Cr/Cb is between 1-15, the internal circuit will clamp these values to 16. When the Cr value is 0 and 255, the internal circuit will set the Cr value as 112. When Cb value is 0 and 255, the internal circuit will set the Cb value as 225. Thus when the external video source is reset to 0 or 255, the color at video output will appear blue.
7.2
Mode selection
There are 7 mode registers which can be programmed by setting the four MODE[3:0] pins and the MASTER pin. The following table illustrates the arrangement of the 7 mode registers.
PIN DESCRIPTION THE MASTER PIN MODE[3] MODE[2] MODE[1] MODE[0]
0 1
MODE REGISTER NAME
YCSWAP EFIELD
SETUP PAL625
PALSA INTERLACED
-SQUARE
SET TO 0
SET TO 1
COMMENTS
EFIELD
The VSYNCN pin will output field signal. Low at VSYNCN pin for even field, high for odd field 525-line operation will be select Non-interlace operation will be select CCIR-601 timing is selected.
The VSYNCN pin will output normal vertical synchronization signal. The 625-line operation will be select The interlace operation will be select The square pixel timing is selected.
Master mode only. Master mode only. Master mode only. Master mode only.
PAL625 INTERLACED SQUARE
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W55VG680
Continued.
MODE REGISTER NAME
SET TO 0
SET TO 1
COMMENTS
YCSWAP SETUP
Do not swap Y and Cr/Cb Disable the 7.5 IRE setup When PAL625 register is set to high, PAL-BDGHI mode is selected. When PAL625 register is set to low, NTSC mode is selected.
Swap Y and Cr/Cb sequence Enable the 7.5 IRE setup When PAL625 register is set to high, PAL-Nc mode is selected. When PAL625 register is set to low, PAL-M mode is selected.
Slave mode only. Slave mode only. Slave mode only.
PALSA
At slave mode, the W55VG580 will automatically detect the input video timing. The EFIELD, PAL625, INTERLACE, and SQUARE register will not be necessary. W55VG680 will not generate synchronization signals which are from external. The control timing, for the detail, please reference table 2. At master mode, the MODE[3:0] pins will set EFIELD, PAL625, INTERLACED and SQUARE registers. The YCSWAP, SETUP, and PALSA registers can be programmed by switching the W55VG580 to slave mode, then back to the master mode. At power-on, the YCSWAP, SETUP, and PALSA are set to zero. For example, please reference the waveform of notice as below, the EFIELD, PAL625, INTERLACE, and SQUARE can be set when master pin go low, and the internal register will latch the setting data.
Note: Configure waveform
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
7.3 The Relationship between TV System and Bit allocation
BITS[3:0]={ PALSA, PAL625, SQUARE, INTERLACE } FL: Line Rate FP: Pixel Rate FSC: Sub-carrier Frequency
BITS[3:0] FORMAT PIXEL X LINE FL FP FSC
0 1 2 3 4 5 6 7 8 9 A B C D E F
M/NTSC, 601, NI M/NTSC, 601, I M/NTSC, S, NI M/NTSC, S, I BDGHIN/PAL, 601, NI BDGHIN/PAL, 601, I BDGHIN/PAL, S, NI BDGHIN/PAL, S, I M/PAL, 601, NI M/PAL, 601, I M/PAL, S, NI M/PAL, S, I Nc/PAL, 601, NI Nc/PAL, 601, I Nc/PAL, S, NI Nc/PAL, S, I
858x262 858x525 780x262 780x525 864x312 864x625 944x312 944x625 858x262 858x525 780x262 780x525 864x312 864x625 944x312 944x625
15734.264 15734.264 15734.264 15734.264 15625.000 15625.000 15625.000 15625.000 15734.264 15734.264 15734.264 15734.264 15625.000 15625.000 15625.000 15625.000
13500000 13500000 12272727 12272727 13500000 13500000 14750000 14750000 13500000 13500000 12272727 12272727 13500000 13500000 14750000 14750000
3579545.00 3579545.00 3579545.00 3579545.00 4433618.75 4433618.75 4433618.75 4433618.75 3575611.49 3575611.49 3575611.49 3575611.49 3582056.25 3582056.25 3582056.25 3582056.25
7.4
Color Space Conversion
The 8-bit 4:2:2 YCrCb data input are linearly interpolated to 4:4:4 format and then converted to YUV format.
7.5
Low-Pass Filter
The U/V signal is low passed by a digital filter specified by CCIR 624.
7.6
Modulator
The U and V color difference signals are modulated by a sub-carrier frequency generated by an internal DTO. After modulation, they are summed together to produce luminance signal.
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W55VG680
7.7 Video Timing
The W55VG680 can operate in master mode and slave mode. This is done by setting the MASTER pin. When the MASTER pin is set to logical low, the W55VG580 operates at slave mode. When The MASTER pin is set to logical high, the W55VG680 operates at master mode. At master mode, the W55VG680 automatically generates the required timing from the CLK input. The HSYNCN and VSYNCN pins are output following the rising edge of CLK. Coincident falling edges of HSYNCN and VSYNCN indicates the beginning of an odd field. A falling edge of VSYNC without a coincident falling edge of HSYNCN indicates the beginning of an even field. At slave mode, the W55VG680 accepts external horizontal and vertical synchronization signals via the HSYNC and VSYNC pins and automatically detects the input video format. The W55VG680 then generates the detected video timing. The W55VG680 automatically calculates the width of the horizontal sync pulse and the start and end of color burst. Color burst is automatically disabled on appropriate lines. Serration and equalization pulses are automatically inserted into appropriate lines.
7.8
Video and Burst Blanking
Video and burst information is automatically disabled according to the Rec. CCIR624.
7.9
Power Down
When the SLEEP pin is logical high, the W55VG680 enters sleep mode. The clock input and DAC outputs are disabled.
7.10 Analog outputs
The output, CVBS_C is an 8-bit D/A converter outputs. This output is specified to drive 37.5 loads. When the SVIDEO pin is connected to high, CVBS_C will output signal which can be interface to the S-Video machine. When the SVIDEO pin is connected to low, the CVBS_C will output composite video.
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
field 1
START of VSYNC
523
524
525
1
2
3
4
5
6
7
8
9
10
21
22
field 2
burst phase
261
262
263
264
265
266
267
268
269
270
271
272
273
284
285
field 3
burst phase
523
524
525
1 field 4
2
3
4
5
6
7
8
9
10
21
22
burst phase
261
262
263
264
265
266
267
268
269
270
271
272
273
284
285
Burst begins with positive half cycle Burst phase=180 relative to B-Y Burst begins with negative-half cycle Burst phase=180 relative to B-Y
Figure 1. NTSC Interlace Video Timing ( SMPTE line conversion rather than CCIR-624 is used)
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W55VG680
START of VSYNC
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
+U phase
field 1 field 5
308
309
310 311
312
313
314
315
316
317
318
319
320
335
336
field 2,6
620
621
622 623
624
625
1
2
3
4
5
6
7
22
23
24
field 3,7
308
309
310
311
312
313
314
315
316
317
318
319
320
335 336
field 4,8
Burst Blanking Interval
field 1,5 field 2,6 field 3,7 field 4,8
Burst phase=135 relative to U +V component Burst phase=225 relative to U -V component
Figure 2.
B,D,G,H,I/PAL Interlace Video Timing
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
START of VSYNC
257 258
259
260
261
262
1
2
3
4
5
6
7
8
17
18
257 258
259
260
261
262
1
2
3
4
5
6
7
8
17
18
Burst begins with positive half cycle Burst phase=180 relative to B-Y Burst begins with negative-half cycle Burst phase=180 relative to B-Y
Figure 3.
NTSC Non-interlace Video Timing
START of VSYNC
307
308 309
310
311
312
1
2
3
4
5
6
7
22
23
307
308
309
310
311
312
1
2
3
4
5
6
7
22
23
Burst phase=135 relative to U +V component Burst phase=225 relative to U -V component
Figure 4.
PAL Non-interlace Video Timing
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W55VG680
8. ELECTRICAL CHARACTERISTICS
Recommended Operating Conditions
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Power Supply Ambient Operating Temperature DAC Output Load External Voltage Reference
VAA TA RL VREF
3.0
0 50 1.245
3.30
--1.275
3.6
70 -1.295
V
C
V
Absolute Maximum Ratings
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Power Supply ( Measured to ground) Ambient Operating Temperature Voltage on Any Signal Pin Storage Temperature Junction Temperature
VAA TA -TS TJ
--55 GND-0.5 -65 --
------
3.6
125 VAA+0.5 +150 +150
V
C
V
C
C
Note: This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any pin that exceeds the power supply voltage by more than +0.5V can cause destructive latch up.
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
9. DC CHARACTERISTICS
(Recommended operating conditions using external voltage reference with RSET=180 , VREF=1.275V, NTSC CCIR601 operation and clock frequency= 27 MHz at 25 C , +5V)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
VAA Supply Current Video D/A Resolution Integral Nonlinearity Differential Nonlinearity Maximum Output Current Output Compliance Video level Error Using External Reference Using Internal Reference Full-Scale DAC Output Digital Inputs Input High Voltage Input Low Voltage Input High current (Vin=2.4V) Input Low current (Vin=0.4V) Digital Outputs Output High Voltage (IOH=-400uA) Output Low Voltage (IOL=3.2mA) Three-State Current VREF Output Voltage VREF Output current
IAA@ 70 C IAA@ 0 C INL DNL VOC VIH VIL IIH IIL
8 0 2.0 GND-0.5 -
50 50
8 182.5 -
tbd tbd 8 +/- 1 +/- 1 26.04 1.5 5 10 VAA+0.5 0.8 1 -1
mA mA Bits LSB LSB mA V % % IRE V V uA uA
VOH VOL IOZ VREF IREF
2.4 1.064 -
1.275 10 0.4 50 1.298 -
V V uA V uA
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W55VG680
10. AC CHARACTERISTICS
(Recommended operating conditions using external voltage reference with RSET=180 , VREFIN=1.235V, NTSC CCIR601 operation and clock frequency=27 MHz at 25 C, +5V)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Luminance Bandwidth Chrominance Bandwidth Differential Gain Differential Phase SNR Hue Accuracy Color Saturation Accuracy Analog Output Delay Analog Output Rise Time Analog Output Settling Time Pixel/Control Setup Time Pixel/Control Hold Time Control Output Delay Time CLOCK Frequency CLOCK Pulse Width Low Time CLOCK Pulse Width High Time Pipeline Delay
5 1 2 3 Fin 4
0 6 24.54 10 10 -
Fin/4 1.3 1 1 60 1.5 1.5 30 3 30 15 27 28
3 3 29.5 -
MHz MHz % dB % ns ns ns ns ns ns MHz ns ns Clocks
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
Color/Level Peak Chroma White
HSYNC 1 1
BLANK 1 1
mA 33.06 27.22
V 1.240 1.021
IRE 134 100
Peak Burst Black Blank Peak Burst
1 1 1 1
1 1 0 0
11.97 9.6 8.16 4.37
0.449 0.360 0.306 0.164
20 7.5 0 -20
SYNC
0
0
0.53
0.020
-40
Note: 37.5 load is used. VREF = 1.275V, RSET = 180 . 100% amplitude, 100% saturation are shown. RS170A levels and tolerance are assumed.
Figure 5. NTSC Composite Output Waveform
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W55VG680
Color/Level Peak Chroma White
HSYNC BLANK 1 1 1 1
mA 34.16 27.76
V 1.281 1.041
IRE 133 100
Peak Burst Black/Blank Peak Burst
1 1 1
1 0 0
12.8 8.72 4.64
0.480 0.327 0.174
21.5 0 -21.5
SYNC
0
0
0.53
0.02
-43
Note: 37.5 load is used. VREF = 1.275V, RSET = 180 . 100% amplitude, 100% saturation are shown. CCIR 624 levels and tolerance are assumed.
Figure 6. PAL-BDGHI Composite Output Waveform
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
Analog Power Plane VAA COM VREF AGND FSADJ RSET 75 c5 Z1 c4 c1 L1 R1 c7 c6 To Power Supply Ground +3.3V (VDD)
C VAA
To Video Connectors (75 load) =
LOW PASS FILTER
To Connector GND
PART NUMBER
VALUE
VENDOR NUMBER
c1, c4, c5, c6 c7 L1 R1 RSET Z1
0.1uF (Ceramic) 47uF Ferrite bead 1KW (5% ) 1% Metal Film 1.2V Zener Diode
Erie RPE112Z5U104M50V Mallory CSR13F476KM Fair-Rite 2743001111 Dale CMF-55C LM358BZ-1.2
Note: 1. The vendor number is only for reference. 2. RSET is determined by (Iout=full scale output current)
Re xt ( ) = 4080 * VREF (V ) / Iout ( mA )
Figure 7.
Typical connection diagram and part list (using external voltage reference)
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W55VG680
Analog Power Plane VAA COM VREF AGND FSADJ RSET c4 c1 c5 Z1 75 L1 c7 c6 To Power Supply Ground +3.3V (VDD)
C VAA
To Video Connectors (75 load)
=
LOW PASS FILTER
To Connector GND
PART NUMBER
VALUE
VENDOR NUMBER
c1, c4, c5, c6 c7 L1 RSET
0.1uF (Ceramic) 47uF Ferrite bead 1% Metal Film
Erie RPE112Z5U104M50V Mallory CSR13F476KM Fair-Rite 2743001111 Dale CMF-55C
Note: 1. The vendor number is only for reference. 2. RSET is determined by (Iout=full scale output current)
Re xt ( ) = 4080 * VREF (V ) / Iout ( mA ) Re xt ( ) = 4080 * VREF (V ) / Iout ( mA )
Figure 8. Typical connection diagram and part list (using internal voltage reference)
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
CLOCK
P[7:0] HSYNCN,VSYNCN (slave mode) HSYNCN,VSYNCN (master mode) 1 Analog 2
pixel 0
Pixel 1
4 pixel 1 pixel 0
output
3 5
Figure 9. Video Input and Output Timing
CLOCK
P[7:0]
Cb0
Y0
Cr0
Y1
HSYNCN,VSYNCN
Figure10. Pixel sequence at power on reset (The pixel sequence can be swap by setting the CBSWAP pin and the MODE[3] pin at slave mode)
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W55VG680
Table1. Field Resolution and clock Rates for Various Modes of Operation
OPERATING MODE ACTIVE PIXELS TOTAL PIXELS CLK FREQUENCY (MHZ)
NTSC/PAL-M CCIR601 PAL-B,D,G,H,I,Nc NTSC/PAL-M Square pixel PAL-B,D,G,H,I,Nc Square pixel
720 x 240 720 x 288 640 x 240 768 x 288
858 x 262 864 x 313 780 x 262 944 x 312
27 27 24.545454 29.5
a
b d c e
Table2. Various Video Timing
OPERATION MODE FRONT PORCH (E) HORIZONTAL SYNC WIDTH (B) START OF BURST (C) DURATION OF BURST (D) BACK PORCH (E)
NTSC CCIR601 PAL-M CCIR610 PAL-B CCIR601 PAL-Nc CCIR601 NTSC SQUARE PAL-M SQUARE PAL-B SQUARE PAL-Nc SQUARE
20 20 20 20 18 18 22 22
63 63 63 63 58 58 69 69
72 78 76 76 65 71 83 83
34 34 30 34 31 31 33 37
127 127 142 142 115 115 155 155
Notes: (1) The unit is the number of luminance pixel.
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
11. PACKAGE INFORMATION
TYPE NUMBER PACKAGED AMBIENT TEMPERATURE RANGE NOTE
W55VG680YG W55VG680PG W55VG680H
QFN-32 PLCC-32 Chip form
0~70 C 0~70 C 0~70 C
Lead-Free Lead-Free ---
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W55VG680
12. PACKAGE DIMENSION
12.1 PLCC
SYMBOL
INCHES MIN TYP MAX MIN
MM TYP MAX
A A1 B B1 D D1 D2 E E1 E2 e N Nd Ne
0.1 0.06 0.013 0.026 0.485 0.447 0.39 0.585 0.547 0.49 0.05
0.14 0.095 0.021 0.032 0.495 0.455 0.43 0.595 0.555 0.53
2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.54 1.27 32 7 9
3.56 2.41 0.53 0.81 12.57 11.56 10.92 15.11 14.1 13.46
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W55VG680
12.2 QFN-32
L
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W55VG680
13. APPLICATION CIRCUIT
VCC33 TV_VS TV_HS
C1 0.1u C0603
VDC C2 0.1u C0603
CVBS_Y NC TEST HSYNC VSYNC VDD DGND
R1 160 R0603 1 2 3 4 5 6 7 8 9
32 31 30 29 28 27 26
U1
SVIDEO CBSWAP MASTER MODE3 MODE2 MODE1 MODE0
C4 0.1u C0603
C3
C0603 0.1u
FSADJ COMP VAA VREF_OUT VREF_IN NC CVBS_C AGND SLEEP
CLK D7 D6 D5 D4 D3 D2 D1 D0
25 24 23 22 21 20 19 18 17
XCLK Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y [0..7]
CVBS_C
10 11 12 13 14 15 16 Setting0 Setting1 Setting2 Mode3 Mode2 Mode1 Mode0
W55VG680Y G
Setting[0..2] Mode[3..0]
QFN-32
C5 CVBS_C R2 75 100uF
J1 Video JACK
VDC
VDC L1
VCC33
VDC1 3V3
C6 10uF
FB C7 104p L2 FB C8 10uF
C9 104p
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Publication Release Date: May, 2006 Revision A1.6
W55VG680
14. BILL OF MATERIAL
Item 1 2 3 4 5 6 7 8 9 10 Q'ty. 4 1 2 2 1 2 1 1 1 1 Ref. C1,C2,C3,C4 C5 C8,C6 C7,C9 J1 L1,L2 R1 R2 U1 VDC1 Value 0.1u 100uF 10uF 104p Video JACK FB 160 75 W55VG680YG 3V3
15. DOCUMENT HISTORY
DATE REVISION EDITOR COMMENTS
01/27/2005 02/23/2005 03/20/2005 04/13/2005 06/08/2005
A1 A1.1 A1.2 A1.3 A1.4
Cliff Huang Cliff Huang Cliff Huang Cliff Huang Cliff Huang
Original issue Data pin re-arrangement correct. Update Application content and QFN package dimension. Remove out PLCC packaged. 1. Changed Vref_in to Vref. And typical value is changed to 1.275 from 1.235V. 2. Change Rext formula. 1. REXT change to 180 from 10K. 2. Pin arrangement modified. 3. Modified output driving power, pin 11, as 37.5mW. 1. Edit proof. 2. HSYNCN & VSYNCN change to HSYNC and VSYNC . 3. SVIDEO only Y output. 4. Add Application circuit and Bill of Material.
09/12/2005
A1.5
Cliff Huang
05/17/2006
A1.6
Cliff Huang
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W55VG680
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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Publication Release Date: May, 2006 Revision A1.6

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